AMD's upcoming Zen 6 processors will pack three distinct CPU core types, not two, according to Linux kernel patches that surfaced this week. A newly discovered "Low Power" core joins the existing Performance and Efficiency designs, targeting idle and background workloads on future Medusa APUs.
The patches describe a third core variant that uses the same x86 instruction set as standard Zen 6 and Zen 6C cores. That differentiates AMD's approach from Intel's hybrid architecture, where disparate core designs can create software compatibility headaches.
AMD keeps one ISA across all three core types, letting the operating system treat them as familiar hardware while the processor handles power allocation internally.
AMD identifies the Low Power core through extended CPU topology information exposed to the kernel, according to the patch documentation. The Linux scheduler can then apply appropriate performance-scaling behavior for lighter workloads rather than defaulting to generic handling. The design aims to cut power consumption during idle periods and background tasks without any changes to software compatibility.
The Medusa APU family is expected to be the first platform to combine all three Zen 6 core types. AMD reportedly plans to introduce the Medusa lineup around CES 2027, and the existence of working Linux patches suggests development is well past the planning stage.
The patches land as Linux Kernel 7.2 Release Candidate 1 ships with a record 43 million lines of code. Linus Torvalds announced RC1 on June 28, and the AMDGPU and AMDKFD graphics driver suite alone accounts for 6.3 million lines of that total -- the single largest driver subsystem in the kernel.
Torvalds noted that roughly a third of this update cycle consisted solely of AMD GPU register definitions.
Linux 7.2 stable is expected around late August 2026 if the standard eight-release-candidate cadence holds. The kernel's growing AMD driver footprint, combined with early Zen 6 core topology patches, signals that AMD is laying extensive groundwork in open-source infrastructure for its next-generation silicon well ahead of hardware availability.
