Intel's critical 18A manufacturing technology makes its data center debut with Xeon 6+ "Clearwater Forest" processors packing up to 288 cores, unveiled at Mobile World Congress this week. The new chips represent Intel's first server CPUs built on the company's advanced 18A (1.8nm-class) fabrication process, marking a key moment for the semiconductor giant's manufacturing roadmap.
Clearwater Forest processors succeed the Sierra Forest Xeons launched in 2024 and target telecom operators preparing for AI-driven network upgrades.
Each processor combines up to twelve compute tiles fabricated on Intel's latest 18A node, housing twenty-four energy-efficient Darkmont cores per tile for a maximum of 288 cores per socket. Dual-socket configurations can reach 576 cores in a single server platform.
Intel employs sophisticated packaging technology to assemble these multi-chip designs. Compute tiles stack atop base dies using Foveros Direct 3D interconnects while lateral connections use EMIB bridges. The complete package includes three base tiles manufactured on Intel's previous-generation Intel 3 process and two I/O tiles built on even older Intel 7 technology.
This architectural approach delivers what Intel claims is over one gigabyte of last-level cache, approximately 1,152MB total, to keep data close to hundreds of active cores and reduce dependence on external memory bandwidth.
Telecom infrastructure stands as the primary target market for these high-density processors. Kevork Kechichian, executive vice president of Intel's Data Center Group, emphasized that
"AI in networks isn't 'CPU vs. GPU', it's right compute for the workload."
The strategy keeps network functions, security workloads, enterprise services, and AI inference running on standard server hardware rather than requiring separate accelerators.
Testing by Ericsson demonstrated significant efficiency gains from Clearwater Forest technology. A single 288-core Xeon processor reduced runtime rack power by thirty-eight percent while delivering more than sixty percent better performance per watt compared to previous-generation Sierra Forest systems.
Platform specifications include twelve memory channels supporting DDR5-8000 speeds alongside ninety-six PCIe Gen5 lanes with sixty-four lanes supporting CXL connectivity for accelerator attachment. The processors remain drop-in compatible with existing Xeon server sockets despite their architectural advancements.
Intel positions these extreme core count designs specifically for virtualized radio access networks and edge AI inference workloads as carriers transition toward 5G Advanced and early 6G development.
By combining matrix acceleration through Advanced Matrix Extensions with vRAN Boost offloads and extensive caching in one platform, the CPUs can handle tasks typically requiring separate power-hungry accelerators. The company also showcased Xeon 6 SoC variants at MWC designed for networking and edge segments with up to seventy-two performance cores per chip and integrated Ethernet connectivity reaching two hundred gigabits per second.
Systems based on Clearwater Forest processors will be available later this year according to Intel's announcement timeline.
